SY89874AU buffer equivalent, 2.5ghz any-in to lvpecl programmable clock divider/fanout buffer.
The /RESET input asynchronously resets the divider. In the pass-through function (divide by 1) the /RESET synchronously.
This low-skew, low-jitter device can accept a high-speed (622MHz or higher) LVTTL, LVCMOS, CML, LVPECL, LVDS or HSTL clock input signal and divide down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version.
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